Present complementary metal oxide semiconductor (CMOS) and bipolar-CMOS (BiCMOS) circuits employ electrostatic discharge protection (ESD) circuits to protect against electrostatic discharge due to ordinary human and machine handling. This electrostatic discharge occurs when the semiconductor circuit contacts an object that is charged to a substantially different electrostatic potential of typically several thousand volts. The contact produces a short-duration, high-current transient in the semiconductor circuit. This high current transient may damage the semiconductor circuit through joule heating. Furthermore, high voltage developed across internal components of the semiconductor circuit may damage MOS transistor gate oxide.
Sensitivity of the semiconductor circuit is determined by various test methods. The circuit of FIG. 5 is typically used to determine sensitivity of the semiconductor circuit to human handling.
The test circuit includes a stress voltage supply Vs 500 connected in series with a current limiting resistor 502. A capacitor 506 and resistor 508 emulate a human body resistor-capacitor (RC) time constant. The capacitor 506 is preferably 100 pF, and the resistor 508 is preferably 1500.OMEGA., thereby providing a 150-nanosecond time constant. The semiconductor device or device under test (DUT) is connected to the test circuit at a predetermined external terminal for a selected test pin combination. In operation, a switch 504 selects resistor 502 to initially charge capacitor 506 to stress voltage Vs. Switch 504 then selects a discharge path through resistor 508 and the DUT. A post stress current-voltage measurement determines whether the DUT is damaged. Although this test effectively emulates electrostatic discharge from a human body, it fails to comprehend other common forms of electrostatic discharge. Moreover, the relatively high resistance discharge path of the test circuit drops most of the stress voltage Vs during the ESD test, thereby producing a low-voltage test at the DUT. This low-voltage test fails to develop worst-case internal voltages within the semiconductor circuit that may be inherent with other common forms of ESD.
Referring to FIG. 6, there is another test circuit of the prior art for testing semiconductor circuits under charged-device ESD. This circuit is typically used to determine sensitivity of the semiconductor circuit to ESD under automated manufacturing conditions. The test circuit includes a stress voltage supply Vs 600 connected in series with a current limiting resistor 602. The DUT 606 forms a capacitor 609 above a ground plane 608 that is typically 1-2 pF. A small parasitic resistor 610 and parasitic inductor 612 form a discharge path having an RC time constant typically two orders of magnitude less than the tester of FIG. 5. In operation, a switch 604 selects resistor 602 to initially charge the DUT 606 with respect to ground plane 608 to stress voltage Vs. Switch 604 then connects an external terminal of the DUT to the discharge path through parasitic resistor 610 and parasitic inductor 612. This connection produces a high-voltage, high-current discharge in which a magnitude of the initial voltage across the DUT approaches that of the initial voltage across capacitor 609.
Input protection circuits of the prior art typically provided two-stage input protection to isolate internal circuits from high-voltage transients at an external terminal or bond pad. The prior art circuit of FIG. 3 comprises a primary clamp 302 coupled to external terminal 316. Resistor 304 couples the primary clamp 302 to secondary clamps 306 and 308 and to the control gates of input transistors 310 and 312. The primary and secondary clamps may be any combination of silicon-controlled rectifiers, transistors, diodes or Zener diodes as is well known in the art. Secondary clamps 306 and 308 preferably conduct at a lower voltage than primary clamp 302, thereby isolating internal circuits from potentially destructive voltage levels. In operation, an ESD voltage at external terminal 316 produces a voltage increase at internal terminal 318. This voltage increase activates one of secondary clamps 306 and 308. The activated secondary clamp conducts ESD current, thereby clamping the voltage at terminal 318. This clamped voltage at terminal 318 prevents rupture of the gate oxide of input transistors 310 and 312 and produces a voltage drop across resistor 304. The ESD voltage at external terminal 316 continues to rise until primary clamp 302 is activated. Primary clamp 302 then conducts a majority of the ESD current for the duration of the ESD event.
Normal operation of the circuit of FIG. 3, however, is compromised by resistor 304 and the capacitance of secondary clamps 306 and 308 and input transistors 310 and 312. Resistor 304 typically has a resistance of 100.OMEGA.. Secondary clamps 306 and 308 and input transistors 310 and 312 typically have a capacitance of 2 pF. A signal transition at external terminal 316, therefore, is delayed at internal terminal 318 by a 200 ps time constant. This delay imposes a significant limitation on high frequency circuit performance. A complete signal transition at internal terminal 318, for example, may be delayed by three time constants or 600 ps from the corresponding transition at external terminal 316. This delay may comprise more than ten percent of total access time for high-speed semiconductor circuits.
Referring to FIG. 4, there is an alternative input protection circuit of the prior art. This circuit preferably includes a single secondary clamp 406. The circuit further includes N-channel transistor 414 connected in series with input transistor 410. A hysterisis circuit, including P-channel transistor 414 and inverter 416, is connected in parallel with N-channel transistor 414. Logic gates such as NAND and NOR input buffer designs also include series transistors to selectively enable the circuit as is well known in the art. These circuits of the prior art include resistor 404 to couple external terminal 420 to internal terminal 422 as previously described. Such alternative embodiments of the prior art are similarly limited during normal circuit operation by the inherent resistance and capacitance (RC) delay of the input circuit.
A reduction in size of resistor 404 to reduce circuit delay will compromise ESD performance of the prior art circuit of FIG. 4. A typical input transistor 412, for example, with a gate oxide thickness of 8 nm may rupture when subjected to an electric field of 12 MV/cm or 9.6 V. A silicon-controlled rectifier (SCR) primary clamp 402 may have an activation voltage of 15 V. A corresponding MOS diode secondary clamp may have an activation voltage of 8 V. An arbitrary reduction in resistance of resistor 404, therefore, would increase current through and eventually destroy secondary clamp 406. Alternatively, a reduction in resistance of resistor 404 would increase the voltage at internal terminal 422 above the 9.6 V rupture voltage between the control gate and source terminal of input transistor 412, thereby destroying input transistor 412.
Referring now to FIG. 7A, there is yet another input protection circuit of the prior art. This circuit is similar to the circuit of FIG. 4 except that N-channel transistor 420 is replaced by NPN bipolar transistor 712. The circuit includes Zenner diode 714 connected between the Vcc voltage supply terminal and the transistor base for biasing the circuit during normal operation. The input protection circuit of FIG. 7B of the prior art is also similar to the circuit FIG. 4 except that the hysterisis circuit, including transistor 414 and inverter 416, is omitted. Furthermore, the N-channel load transistor 420 is replaced by P-channel load transistor 722 having a grounded control gate. As with the circuit of FIG. 4, however, these alternative embodiments of the prior art are also limited during normal circuit operation by the inherent resistance and capacitance (RC) delay of the input circuit.